In the related art, as one type of solid-state imaging devices (image sensor), CMOS (Complementary Metal Oxide Semiconductor) type solid imaging devices are known. Generally, the CMOS-type solid-state imaging devices can be manufactured by using the same manufacturing process as that of CMOS-type integrated circuits. Accordingly, in the manufacturing process of the CMOS-type solid-state imaging devices, an analog circuit and a logic circuit can be manufactured inside the same chip.
Of such CMOS-type solid-state imaging devices, column parallel-type solid-imaging devices are used as mainstream devices in which pixel signals in a specific row are simultaneously read out in the column direction from a pixel array, in which pixels are two-dimensionally arranged, and a parallel process is performed. Regarding a processing circuit arranged on the signal output stage of the column parallel-type solid-state imaging device, various configurations are proposed in the related art (for example, see JP-A-2009-124514).
FIG. 18 schematically illustrates a block circuit configuration of a column parallel-type solid-state imaging device in the related art that is, for example, disclosed in JP-A-2009-124514 and the like.
The solid-state imaging device 300 includes: a pixel array unit 302 that is configured by arranging a plurality of pixels 301 in the row direction and the column direction in a matrix pattern; a row scanning circuit 303; a column scanning circuit 304; and a timing control circuit 305. In addition, the solid-state imaging device 300 includes a reference voltage generating circuit 306 (DAC: Digital to Analog Converter) and an ADC (Analog to Digital Converter) block 307. The ADC block 307 includes a comparator 311, a counter unit 312, and a latch circuit 313 that are disposed for each vertical signal line VSL.
In the solid-state imaging device 300 having the configuration illustrated in FIG. 18, the signal of a reference voltage RAMP output from the reference voltage generating circuit 306 has a waveform in which the voltage level decreases at a predetermined inclination (linear) with respect to time with a predetermined dynamic range (variation width). The voltage levels of the reference voltage RAMP and the pixel signal readout from each vertical signal line VSL are compared with each other by the comparator 311, and a time (comparison time) until both signals intersect is measured by the counter unit 312. Then, the comparison time (counted number) acquired from the counter unit 312 is maintained in the latch circuit 313 and then is output through a horizontal output line 314. Thereafter, the output counted number is converted into a corresponding output code (digital signal).
In addition, in JP-A-2009-124514, the comparator 311 is proposed in which a first amplifier and a second amplifier, which are cascode-connected, and a mirror circuit disposed in parallel with the second amplifier are arranged. Furthermore, in JP-A-2009-124514, in a mirror circuit, a technique is proposed in which, in order to determine the operating point for each column at the time of starting a row operation, a voltage that is initialized and sampled is input to the gate. In JP-A-2009-124514, the mirror circuit is controlled by detecting the output level of the second amplifier, thereby suppressing a change in the analog power source.